Copper is widely used as a power metallization in semiconductor devices. However, when a copper film is subjected to temperature cycling, the copper film undergoes elastic and plastic deformation which induces stress on the surrounding elements such as the barrier, ILD (interlayer dielectric), passivation, etc. The stress induced by the copper film can lead to one or more failure modes such as cracks in the passivation and/or in the device substrate, delamination between the copper film metal and the barrier, etc. The induced stress is strongly dependent on morphology of the power metal after structuring. Hence, improved measures are needed for mitigating the stress induced by copper films used in semiconductor devices.
Moreover, thick copper has low routing density due to low pitch. An increase in routing density can be realized by adding additional routing layers, which includes metal deposition and patterning, ILD deposition for insulation, and via etch to connect the metal layers. This adds to the overall cost of the semiconductor device. For power technologies with thick copper metallization and bonding on active areas, additional softer (e.g. aluminum) layers increase the layout complexity. Copper damascene processes circumvent such problems, but at extremely high additional costs. Hence, improved measures are needed for increasing routing density when using copper metallization in semiconductor devices.